1. Field of the Invention
The present invention relates to a division arithmetic unit. More specifically, the present invention relates to a division arithmetic unit of variable radix.
2. Description of the Related Art
In terms of signal processing, digital circuits perform binary operations, while from the structural view of circuit blocks they can carry out arithmetic operations of any base or radix 4, 10 or 16. The conventional divider is designed to determine the radix of powers of 2 such as radix-4, radix-8 and radix-16. One of the most typical dividers is a so-called SRT divider, taking its name from the initials of Sweeney, Robertson and Tocher who developed the algorithm independently at approximately the same time. The SRT division, a class of non-restoring binary division algorithm, has been designed for floating-point computation. The term “non-restoring” refers to the fact that partial remainders are allowed to range freely through the interval (−1, 1), rather than being restored to the positive realm before proceeding to the next step. The SRT division algorithm does not require addition/subtraction operations needed in the classical non-restoring division techniques, just adds a shift operation by making one bit of the quotient to be 0, and makes use of a redundant quotient digit by reducing the range of conversion condition in the classical non-restoring algorithm. By using the redundancy features, the bits of comparison constant are minimized and thus the circuit elements for determining the quotient bits are made simple.
The basic recursive equations of the SRT division algorithm are:P1=P0−q1·D1;Pj+1=r·Pj−qj+1·D; 
where, pj is j-th partial remainder, p0 is dividend, r is radix, D is divisor, and qj+1 is quotient bit at (j+1)-th recursive step.
The SRT divider, employed in most high performance floating-point arithmetic units, does not experience degradation of the floating-point arithmetic units due to the use of a multiplier because it is based on the subtraction operation. Typically, radix-4 SRT divider is designed and used in consideration of factors such as the physical area occupied by the circuit elements and operational clock frequency. Dividers of higher radix are employed in the field where higher performance is indispensable and require special techniques (for instance, refer to Milos D. Ercegovac, Tomas Lang and Paolo Montuschi, “Very-high Radix Division with Pre-scaling and Selection by Rounding”, IEEE Trans. On Commuters, Vol. 43, No. 8, pp. 909-918, Aug. 1994).
The radix-4 division is an algorithm to obtain the quotient by accumulating 2-bit quotients per cycle for a single operation of the floating point division. However, the conventional radix-4 SRT divider requires relatively many equations, graphs and algorithms as compared to other division algorithms and it takes longer time to implement because the divider is based on tables. Furthermore, the longer operation time of the conventional radix-4 SRT divider is one of the defects.